Create the First Stage Boot Loader

Introduction

The first stage boot loader loads the clocking information, and then the bitstream onto the FPGA prior to the Kernel being loaded onto the FPGA. Though the FSBL doesn't need to be changed very often, if there is anything that you originally program in one clock domain and change clock domains in a later build, then failing to update the FSBL could lead to unexpected behavior and will possibly damage the board.

Creating a new FSBL

If Xilinx SDK (XSDK) is not already open with the current hardware, follow these preliminary steps:

Open Vivado
Export Hardware & Bitstream
Launch Xilinx SDK

After you have Xilinx SDK open, follow these steps to create a FSBL:

Navigate to File > New > Application Project
Give the project a new name, like FSBL
Click Next
Select Zynq FSBL and click Finish
Wait a few minutes to allow the project to build

In the event that it doesn't successfully build - close XSDK, and Vivado

Click the drop down for the fsbl project (not fsbl_bsp)
Click the drop down on src
Open lscript.ld
Select the Add Memory button in the main workspace, and add the following address:

Name	Base Address	Size
ps7_ddr_0_S_AXI_BASEADDR	0x00100000	0x1FF00000

Save the project and XSDK will automatically rebuild the FSBL
The fsbl.elf file will be stored in: <Project_name.sdk>/fsbl/debug